Technological innovations in semiconductor device fabrication are driving market demands for solutions for higher speed, higher integration density and lower power applications. In order to fulfill this requirement wafers or semiconductor elements in general can be stacked. One possibility to electrically connect such stacked wafers or semiconductor elements includes forming through vias in the wafers or semiconductor elements to achieve an electrical connection from a backside of a wafer or semiconductor element to a main side or upper side comprising electrical circuitry. During the formation of a through via a couple of difficulties may arise. For example, one difficulty may be that if the through via process is applied at the very beginning of the wafer processing a metallic filling of the “wafer holes” or through vias or a highly doped filling of such wafer holes would not be compatible with the following semiconductor fabrication process. Otherwise, complex sealing processes of such wafer holes for the highly doped material or metal would be necessary. If the through via process is applied at the very end of the semiconductor processing another difficulty may arise. In this case, for example, the temperature budget, necessary for an appropriate isolation of the wafer substrate to a through hole via filling, could damage the semiconductor devices of the integrated circuit, which is formed in the wafer substrate at this stage of wafer processing.
So far, solutions integrating the through via process in a overall integrated wafer process, for example, in a complementary-metal-oxide semiconductor (CMOS) process or bipolar-complementary-metal-oxide semiconductor (BiCMOS) may result in a loss of process modularity. In this case the through via process and logic process cannot be separated which may cause problems disadvantageously concerning fabrication equipment, yield loss and so on.
Using partially preprocessed through vias with a polysilicon filling, through vias may be opened with wafer grinding at process end. In this case, a complex sealing of the doped polysilicon is necessary to prevent the following semiconductor process steps from contamination. Normally no metal filling of the through vias is possible without a highly complex and risky sealing of the metal. Alternatively, highly doped substrates may be used with integrated through vias. Such highly doped substrates may be used at the beginning of the integrated process to form the electrical devices of the integrated circuits. But due to device isolation issues such highly doped substrates are hardly compatible or even not compatible to integrated CMOS or BiCMOS processes without additional effort.
Therefore, there is a demand for an improved method for forming a through via in a semiconductor element.